Description

The app is a complete free handbook of VLSI with diagramsandgraphs. It is part of electronics & communicationsengineeringeducation which brings important topics, notes, news& blog onthe subject. Download the App as quick reference guide& ebookon this electronics & communications engineeringsubject. Theapp covers more than 90 topics of VLSI Design indetail. Thesetopics are divided in 5 units. You can very easilypass and succeedin your exams or interviews, the app provides quickrevision andreference to the topics like a detailed flash card.Each topic iscomplete with diagrams, equations and other forms ofgraphicalrepresentations for easy understanding. Some of topicsCovered inthis application are: 1. Semiconductor memories:Introduction andtypes 2. Read Only Memory (ROM) 3. Threetransistor DRAM cell 4.One transistor DRAM Cell 5. Flash memory 6.Low - Power CMOS LogicCircuits: Introduction 7. Design of CMOSinverters 8. MOS Inverters: introduction to switchingcharacteristics 9. Scan-BasedTechniques 10. Built-In Self Test(BIST) Techniques 11. Historicalprospective of VLSI Design :Moore's Law 12. Classification of CMOSdigital circuit types 13. ACircuit Design Example 14. VLSI Designmethodologies 15. VLSI Designflow 16. Design Hierarchy 17. Conceptof regularity, modularity andlocality 18. CMOS fabrication 19.Fabrication Process Flow : BasicSteps 20. Fabrication of the nMOStransistor 21. CMOS fabrication :p-well process 22. CMOSfabrication : n-well process 23. CMOSfabrication : twin tubprocess 24. Stick diagrams and mask layoutdesign 25. MOStransistor : physical structure 26. The MOS Systemunder ExternalBias 27. Structure and operation of MOSFET 28. Thethresholdvoltage 29. Current voltage characteristics of MOSFET 30.Mosfetscaling 31. Effects of scaling 32. Small Geometry Effects 33.MOSCapacitances 34. MOS inverter 35. Voltage transfercharacteristics(VTC) of MOS inverter 36. Inverters with n-typeMOSFET load 37.Resistive load inverter 38. Design of Depletion-LoadInverters 39.CMOS inverter 40. Delay time definitions 41.Calculation of DelayTimes 42. Inverter Design with Delay Constrains: Example 43.Combinational MOS Logic Circuits : introduction 44.MOS LogicCircuits with Depletion nMOS Loads : Two-Input NOR Gate45. MOSLogic Circuits with Depletion nMOS Loads : GeneralizedNORstructure with multiple inputs 46. MOS Logic CircuitswithDepletion nMOS Loads : Transient analysis of NOR gate 47. MOSLogicCircuits with Depletion nMOS Loads : Two-Input NAND Gate 48.MOSLogic Circuits with Depletion nMOS Loads : GeneralizedNANDstructure with multiple inputs 49. MOS Logic CircuitswithDepletion nMOS Loads : Transient analysis of NAND gate 50.CMOSlogic circuits : NOR2 (two input NOR ) gate 51. CMOS NAND2(twoinput NAND) gate 52. Layout of Simple CMOS Logic Gates 53.ComplexLogic Circuits 54. Complex CMOS Logic Gates 55. Layout ofComplexCMOS Logic Gates 56. AOI and OAI Gates 57. Pseudo-nMOS Gates58.CMOS Full-Adder Circuit & carry ripple adder 59.CMOSTransmission Gates (Pass Gates) 60. ComplementaryPass-TransistorLogic (CPL) 61. Sequential MOS logic Circuits :Introduction 62.Behavior of Bistable Elements 63. The SR LatchCircuit 64. ClockedSR Latch 65. Clocked JK Latch 66. Master-SlaveFlip-Flop 67. CMOSD-Latch and Edge-Triggered Flip-Flop 68. DynamicLogic Circuits :Introduction 69. Basic Principles of PassTransistor Circuits Alltopics are not listed because of characterlimitations set by thePlay Store.